Solid-state imaging device, method of manufacturing the same, and electronic apparatus

ABSTRACT

A solid-state imaging device includes an Si substrate in which a photoelectric conversion unit that photoelectrically converts visible light incident from a back surface side is formed, and a lower substrate provided under the Si substrate and configured to photoelectrically convert infrared light incident from the back surface side.

CROSS REFERENCE TO RELATED APPLICATIONS

This application is a continuation of U.S. patent application Ser. No.15/784,793, filed Oct. 16, 2017, which is a continuation of U.S. patentapplication Ser. No. 15/054,677, filed Feb. 26, 2016, now U.S. Pat. No.9,831,284, which is a continuation of U.S. patent application Ser. No.14/524,182, filed Oct. 27, 2014, now U.S. Pat. No. 9,312,300, whichclaims the benefit of Japanese Priority Patent Application JP2013-228328 filed Nov. 1, 2013, the entire contents of which areincorporated herein by reference.

BACKGROUND

The present disclosure relates to a solid-state imaging device, a methodof manufacturing the same, and an electronic apparatus, and moreparticularly, to a solid-state imaging device, a method of manufacturingthe same, and an electronic apparatus that enable infrared light andvisible light to be separately obtained.

In Japanese Unexamined Patent Application Publication No. 2004-103964, asubstrate for infrared light reception is affixed to a back surface of asolid-state imaging element, and a switch is switched to an infraredmode to obtain infrared rays through bias, as proposed.

Meanwhile, in a CMOS image sensor (hereinafter, the CMOS image sensor isreferred to as a CIS) of a backside illumination type, a substrate witha wiring layer is turned over to affix a substrate support. In thebackside illumination type CIS, a wafer is polished by chemicalmechanical polishing (CMP) to form a silicon (Si) layer having athickness of about 10 μm to 20 μm (see Japanese Patent No. 3759435).Currently, the Si layer has a thickness of several μm, and a normal Siwafer is used for the substrate support.

SUMMARY

However, in the former solid-state imaging element, it is difficult toseparately obtain visible light and infrared light since there is nocircuit between two substrates. In addition, in the latter backsideillumination type CIS, since the Si layer is thin, the visible light isobtained. However, it is difficult to obtain the infrared light.

It is desirable to separately obtain visible light and infrared light.

According to an embodiment of the present technology, there is provideda solid-state imaging device including an Si substrate in which aphotoelectric conversion unit that photoelectrically converts visiblelight incident from a back surface side is formed; and a lower substrateprovided under the Si substrate and configured to photoelectricallyconvert infrared light incident from the back surface side.

The lower substrate is formed of a compound semiconductor.

An infrared electrode comes in contact with the Si substrate side of thelower substrate, and a lower electrode comes in contact with the outerside of the lower substrate.

A visible light reading circuit configured to read the visible light andan infrared light reading circuit configured to read the infrared lightare formed in the Si substrate.

The infrared electrode is formed in a ring shape.

The visible light reading circuit and the infrared light reading circuitare formed in a position substantially overlapping the infraredelectrode.

The infrared electrode is formed to be transparent.

The lower substrate is formed of silicon, and includes transistors andwirings.

The lower substrate is an n-type substrate.

The Si substrate and the lower substrate form a laminated structure.

A visible light reading circuit configured to read the visible light isformed in the Si substrate, and an infrared light reading circuitconfigured to read the infrared light is formed in the lower substrate.

The infrared light reading circuit is provided in a positionsubstantially overlapping the visible light reading circuit.

According to another embodiment of the present technology, there isprovided a method of manufacturing a solid-state imaging device, themethod including: forming, by a manufacturing device, a photoelectricconversion unit that photoelectrically converts visible light incidentfrom a back surface side, in an Si substrate; and affixing, by amanufacturing device, a lower substrate that photoelectrically convertsinfrared light incident from the back surface side, under the Sisubstrate.

According to still another embodiment of the present technology, thereis provided an electronic apparatus including: a solid-state imagingdevice including an Si substrate in which a photoelectric conversionunit that photoelectrically converts visible light incident from a backsurface side is formed, and a lower substrate provided under the Sisubstrate and configured to photoelectrically convert infrared lightincident from the back surface side; a signal processing circuitconfigured to process an output signal output from the solid-stateimaging device; and an optical system configured to cause the visiblelight and the infrared light to be incident on the solid-state imagingdevice.

The lower substrate is formed of a compound semiconductor.

An infrared electrode comes in contact with the Si substrate side of thelower substrate, and a lower electrode comes in contact with the outerside of the lower substrate.

A visible light reading circuit configured to read the visible light andan infrared light reading circuit configured to read the infrared lightare formed in the Si substrate.

The infrared electrode is formed in a ring shape.

The visible light reading circuit and the infrared light reading circuitare formed in a position substantially overlapping the infraredelectrode.

The infrared electrode is formed to be transparent.

The lower substrate is formed of silicon, and includes transistors andwirings.

In the embodiment of the present technology, the photoelectricconversion unit that photoelectrically converts the visible lightincident from the back surface side is formed in the Si substrate, andthe lower substrate that photoelectrically converts the infrared lightincident from the back surface side is affixed under the Si substrate.

In the other embodiment of the present technology, an output signaloutput from the solid-state imaging device in which the photoelectricconversion unit that photoelectrically converts the visible lightincident from the back surface side is formed in the Si substrate andthe lower substrate that photoelectrically converts the infrared lightincident from the back surface side is affixed under the Si substrate isprocessed by the signal processing circuit, and the visible light andthe infrared light are incident on the solid-state imaging devicethrough the optical system.

According to the embodiments of the present technology, it is possibleto obtain the visible light and the infrared light. Further, accordingto the embodiments of the present technology, it is possible toseparately obtain the visible light and the infrared light.

In addition, the effects described in the present specification are onlyillustrative, and the effects of the present technology are not limitedto the effects described in the present specification and there may beadditional effects.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a block diagram illustrating an example of a schematicconfiguration of a solid-state imaging device to which an embodiment ofthe present technology is applied;

FIG. 2 is a cross-sectional view illustrating an example of a structureof a pixel area and a peripheral circuit portion of a solid-stateimaging device of a backside illumination type;

FIG. 3 is a cross-sectional view illustrating an example of aconfiguration of a pixel of a solid-state imaging device of anembodiment of the present technology;

FIG. 4 is a diagram illustrating an example of an infrared electrode;

FIG. 5 is a diagram illustrating an example of a configuration of avisible light reading circuit;

FIG. 6 is a diagram illustrating an example of a configuration of aninfrared light reading circuit;

FIG. 7 is a diagram illustrating another example of a configuration ofthe infrared light reading circuit;

FIG. 8 is a flowchart illustrating a process of manufacturing asolid-state imaging device;

FIGS. 9A and 9B are diagrams illustrating a process of manufacturing asolid-state imaging device;

FIGS. 10A and 10B are diagrams illustrating a process of manufacturing asolid-state imaging device;

FIGS. 11A, 11B and 11C illustrate a basic schematic configuration of asolid-state imaging device according to an embodiment of the presenttechnology;

FIGS. 12A and 12B illustrate a basic schematic configuration of asolid-state imaging device according to an embodiment of the presenttechnology;

FIG. 13 is a cross-sectional view illustrating an example of aconfiguration of a pixel of a solid-state imaging device of anotherembodiment of the present technology;

FIG. 14 is a flowchart illustrating a process of manufacturing thesolid-state imaging device;

FIGS. 15A to 15E are diagrams illustrating a process of manufacturing asolid-state imaging device; and

FIG. 16 is a block diagram illustrating an example of a configuration ofan electronic apparatus of an embodiment of the present technology.

DETAILED DESCRIPTION OF EMBODIMENTS

Hereinafter, forms for carrying out the present disclosure (hereinafterreferred to as embodiments) will be described. In addition, descriptionwill be given in the following order.

0. Example of schematic configuration of solid-state imaging device

1. First embodiment (backside illumination type CIS (CMOS image sensor))

2. Second embodiment (backside illumination type laminated CIS)

3. Third embodiment (electronic apparatus)

0. Example of schematic configuration of solid-state imaging device

Example of Schematic Configuration of Solid-State Imaging Device

FIG. 1 illustrates an example of a schematic configuration of an exampleof a CMOS (Complementary Metal Oxide Semiconductor) solid-state imagingdevice applied to each embodiment of the present technology.

A solid-state imaging device (element chip) 1 includes a pixel area(so-called imaging area) 3 in which a plurality of pixels 2 eachincluding a photoelectric conversion element are arranged regularlytwo-dimensionally in a semiconductor substrate 11 (for example, asilicon substrate), and a peripheral circuit portion, as illustrated inFIG. 1.

The pixel 2 includes the photoelectric conversion element (for example,a photodiode), and a plurality of pixel transistors (so-called MOStransistors). The plurality of pixel transistors, for example, caninclude three transistors of a transfer transistor, a reset transistorand an amplification transistor or can include four transistors,including a selection transistor in addition to the three transistors.Since an equivalent circuit of each pixel (unit pixel) 2 is the same asa general one, detailed description will be omitted herein.

In addition, the pixel 2 can also have a pixel-shared structure. Thepixel-shared structure includes a plurality of photodiodes, a pluralityof transfer transistors, one shared floating diffusion, and one sharedone of each of other pixel transistors.

The peripheral circuit portion includes a vertical driving circuit 4,column signal processing circuits 5, a horizontal driving circuit 6, anoutput circuit 7, and a control circuit 8.

The control circuit 8 receives an input clock or data indicating, forexample, a mode of operation, and outputs data such as internalinformation of the solid-state imaging device 1. Specifically, thecontrol circuit 8 generates a clock signal or a control signal that is areference of operations of the vertical driving circuit 4, the columnsignal processing circuits 5, and the horizontal driving circuit 6 basedon a vertical synchronizing signal, a horizontal synchronization signal,and a master clock. Also, the control circuit 8 inputs these signals tothe vertical driving circuit 4, the column signal processing circuits 5,and the horizontal driving circuit 6.

The vertical driving circuit 4 includes, for example, a shift register,and selects a pixel driving wiring and supplies a pulse for driving thepixel 2 to the selected pixel driving wiring to drive the pixels 2 inunits of rows. Specifically, the vertical driving circuit 4 selectivelyscans the respective pixels 2 of the pixel area 3 in the verticaldirection sequentially in units of rows, and supplies a pixel signal tothe column signal processing circuit 5 based on signal charges generatedaccording to an amount of light reception in the photoelectricconversion element of each pixel 2 through a vertical signal line 9.

The column signal processing circuit 5 is arranged in, for example, eachcolumn of the pixels 2, and performs signal processing such as noisereduction in each column on signals output from the pixels 2 in one row.Specifically, the column signal processing circuit 5 performs signalprocessing such as correlated double sampling (CDS) for removing a fixedpattern noise specific to the pixel 2, signal amplification, andanalog/digital (A/D) conversion. A horizontal selective switch (notillustrated) is connected and provided between an output stage of thecolumn signal processing circuit 5 and a horizontal signal line 10.

The horizontal driving circuit 6 includes, for example, a shiftregister, and sequentially outputs horizontal scanning pulses tosequentially select the respective column signal processing circuits 5,and outputs a pixel signal from each of the column signal processingcircuits 5 to the horizontal signal line 10.

The output circuit 7 performs signal processing on the signals suppliedsequentially through the horizontal signal line 10 from the respectivecolumn signal processing circuits 5, and outputs a resultant signal. Theoutput circuit 7 may perform, for example, only buffering or mayperform, for example, black level adjustment, column variationcorrection, or various digital signal processing.

An input and output terminal 12 is provided to exchange signals with theoutside.

Example of Cross-Section of Solid-State Imaging Device

FIG. 2 is a cross-sectional view illustrating an example of a structureof the pixel area and the peripheral circuit portion of the solid-stateimaging device. In the example of FIG. 2, an example of the solid-stateimaging device of a backside illumination type is shown.

In the solid-state imaging device of FIG. 2, a wafer is polished bychemical mechanical polishing (CMP) to form a silicon (Si) layer (anelement layer) 31 having a current thickness of about 3 μm. A lightshielding film 33 is formed on one-surface side of this Si layer with anSiO₂ film 32 interposed therebetween.

The light shielding film 33 is laid out in consideration of only anoptical element, unlike wirings. An opening 33A is formed in this lightshielding film 33. A silicon nitride film (SiN) 34 is formed as apassivation film on the light shielding film 33, and a color filter 35and an on-chip lens (OCL) 36 are formed over the opening 33A.

In other words, this is a pixel structure in which light incident fromthe one-surface side of the Si layer 31 is guided to a light receivingsurface of a photodiode 37 formed in the Si layer 31 via the OCL 36 andthe color filter 35. A wiring layer 38 in which transistors or metalwirings are formed is formed on the other-surface side of the Si layer31, and a substrate support 39 is affixed beneath the wiring layer 38.

1. First Embodiment (Backside Illumination Type CIS)

Example of Configuration of Pixel of Solid-State Imaging Device

FIG. 3 is a schematic view of one pixel of the solid-state imagingdevice according to an embodiment of the present technology.

In the pixel 2 of an example of FIG. 3, a photodiode 56 or a transistoris provided in a silicon (Si) substrate 51, similar to the solid-stateimaging device of FIG. 2. A passivation film 52 is formed on the Sisubstrate 51. In addition, in the example of FIG. 3, while only thispassivation film 52 is shown on the incidence-surface side (on the upperside in FIG. 3), an on-chip color filter 35 or an OCL 36 as illustratedin FIG. 2 may be formed. In addition, since the incidence surface is aback surface at the time of formation of the wiring layer and is formedto be turned over, the solid-state imaging device 1 is called a backsideillumination type.

A wiring layer 53 is formed beneath the Si substrate 51. A transistor ora wiring is provided in the wiring layer 53. In the Si substrate 51 orthe wiring layer 53 beneath the Si substrate 51, an infrared lightreading circuit 58 is formed on one side (left in FIG. 3), and a visiblelight reading circuit 59 is formed on the other side (right in FIG. 3).In addition, an infrared electrode 57 for making contact with a lowersubstrate 54 is provided to come in contact with the lower substrate 54on the side facing the lower substrate 54 in the wiring layer 53. Theinfrared electrode 57 is formed in a ring shape (to be hollow) not toobstruct incidence of the infrared light from the incidence surface (theback surface), as illustrated in FIG. 4.

In the example of FIG. 4, an example of the ring-shaped infraredelectrode 57 in the case of 2×2 pixels is shown. A contact 61 forleading to the infrared light reading circuit 58 is formed on the lowerleft side of each infrared electrode 57.

Infrared light incident from the incidence-surface (back-surface) sidepasses through a hollow portion of this ring shape. For example, copperor titanium is used for the infrared electrode 57.

In addition, a shape of the infrared electrode 57 is not limited to thering shape as long as the shape does not obstruct the incidence of theinfrared light. For example, the infrared electrode 57 may be atransparent electrode, such as an indium tin oxide (ITO) or a zinc-basedmaterial. When the infrared electrode 57 includes the transparentelectrode, the infrared electrode 57 may not be a ring shape or may be ashape with no hollow portion (for example, a square).

In the Si substrate 51, the infrared light reading circuit 58 and thevisible light reading circuit 59 are arranged in positions substantially(approximately) overlapping the ring-shaped infrared electrode 57.

Further, the lower substrate 54 is a substrate corresponding to thesubstrate support 39 of FIG. 2, but includes a substrate thatphotoelectrically converts the infrared light. A lower electrode 55 isprovided to come in contact with the lower substrate 54 on a surface ofthe lower substrate 54 on the side (outer side) opposite to the wiringlayer.

In addition, while the lower substrate 54 may be an Si substrate, it ispreferable to use a compound semiconductor such as indium galliumarsenide (InGaAs), indium antimonide (InSb), or mercury cadmiumtelluride (HgCdTe) to form the lower substrate 54. The use of thecompound semiconductor for the lower substrate 54 enables the infraredlight to be photoelectrically converted in a shallow place of the lowersubstrate 54, thus increasing resolution of the infrared light.

In the pixel 2 configured in this way, most of the visible lightincident from the incidence surface (back surface) is photoelectricallyconverted by the photodiode 56 provided in the Si substrate 51 having athickness ranging from 2 μm to 4 μm and read by the visible lightreading circuit 59.

On the other hand, most of the infrared light incident from theincidence surface (back surface) penetrates the Si substrate 51 in thepixel 2, passes through the hollow portion of the infrared electrode 57,is photoelectrically converted in the lower substrate 54, and is read inthe infrared light reading circuit 58.

In addition, as described above with most of the visible light and mostof the infrared light, a part of the visible light is not incident onthe photodiode 56 and a part of the infrared light stops in otherportions before entering the lower substrate 54. Accordingly, correctionmay be performed after the photoelectric conversion.

With the configuration as described above, in the solid-state imagingdevice of a backside illumination type, the visible light and theinfrared light can be obtained at substantially the same time (that is,separately). In addition, the visible light and the infrared light canbe separately obtained.

Example of Configuration of Visible Light Reading Circuit

FIG. 5 is a diagram illustrating an example of a configuration of thevisible light reading circuit of the pixel. In addition, in the exampleof FIG. 5, transistors in FIG. 5 are all negative channel metal oxidesemiconductor (NMOS) ones. The same applies to transistors in thedrawings below.

The visible light reading circuit 59 of the pixel 2 includes, forexample, a photodiode PD as a photoelectric conversion element, asillustrated in FIG. 5. The visible light reading circuit 59 has aconfiguration in which four transistors of a transfer transistor Trf1,an amplification transistor Amp, a selection transistor Se1, and a resettransistor Rst are included as active elements for one photodiode PD.

The photodiode PD has a grounded anode, and photoelectrically convertsthe incident light into an amount of charges (here, electrons) accordingto an amount of light. The transfer transistor Trf1 is connected betweena cathode of the photodiode PD and a floating diffusion FD, and atransfer signal is applied to a gate thereof through a transfer wiring(not illustrated). Accordingly, the electrons resulting from thephotoelectric conversion in the photodiode PD are transferred to thefloating diffusion FD.

A gate of the amplification transistor Amp is connected to the floatingdiffusion FD. This amplification transistor Amp is connected to thevertical signal line SL via the selection transistor Se1, andconstitutes a source follower with a constant current source outside thepixel. Also, a selection signal is applied to a gate of the selectiontransistor Se1 through a selection wiring (not illustrated), and theselection transistor Se1 is turned on. In this case, the amplificationtransistor Amp amplifies a potential of the floating diffusion FD andoutputs a voltage according to the potential to the vertical signal lineSL. The vertical signal line SL transfers the voltage output from eachpixel to the column signal processing circuit 5 of FIG. 1.

The reset transistor Rst is connected between a power supply Vdd and thefloating diffusion FD, and a reset signal is applied to a gate thereofthrough a reset wiring (not illustrated) to reset the potential of thefloating diffusion FD to a potential of the power supply Vdd.

Example of Configuration of Infrared Light Reading Circuit

FIG. 6 is a diagram illustrating an example of a configuration of theinfrared light reading circuit of the pixel. In the case of an exampleof FIG. 6, an example in which, in the lower substrate 54, an electricfield is applied so as to guide holes to the floating diffusion FD isshown.

The infrared light reading circuit 58 of the pixel 2 includes, forexample, the lower substrate 54 of FIG. 3 as a photoelectric conversionunit, as illustrated in FIG. 6. The infrared light reading circuit 58has a configuration in which three transistors of an amplificationtransistor Amp, a selection transistor Se1, and a reset transistor Rstare included as active elements for one lower substrate 54.

The lower substrate 54 is connected between the lower electrode 55 andthe floating diffusion FD. Also, the lower electrode 55 is set to a highvoltage and the floating diffusion FD is reset to ground so as to guidethe holes to the floating diffusion FD.

A gate of the amplification transistor Amp is connected to the floatingdiffusion FD, as in the example of FIG. 5. This amplification transistorAmp is connected to the vertical signal line SL via the selectiontransistor Se1, and constitutes a source follower with a constantcurrent source outside the pixel. Also, a selection signal is applied toa gate of the selection transistor Se1 through a selection wiring (notillustrated), and the selection transistor Se1 is turned on. In thiscase, the amplification transistor Amp amplifies a potential of thefloating diffusion FD and outputs a voltage according to this potentialto the vertical signal line SL. The vertical signal line SL transfers avoltage output from each pixel to the column signal processing circuit 5of FIG. 1.

The reset transistor Rst is connected between the ground and thefloating diffusion FD, and a reset signal is applied to a gate thereofthrough a reset wiring (not illustrated) to reset the potential of thefloating diffusion FD to the ground.

In this example, a technology for providing a hole injection barrier onthe lower electrode 55 side of the lower substrate 54 and an electroninjection barrier on the infrared electrode 57 side, for example, toreduce a dark current can be used.

In addition, the infrared light reading circuit is not limited to theexample of FIG. 6 and may be the same as that of a normal solid-stateimaging device of a photoelectric conversion film lamination type.

Example of Configuration of Infrared Light Reading Circuit

FIG. 7 is a diagram illustrating another example of the configuration ofthe infrared light reading circuit of the pixel. In the case of theexample of FIG. 7, an example in which, in the lower substrate 54, anelectric field is applied so as to guide electrons to the floatingdiffusion FD is shown.

An infrared light reading circuit 58 of the pixel 2 includes, forexample, the lower substrate 54 of FIG. 3 as a photoelectric conversionunit, as illustrated in FIG. 7. The infrared light reading circuit 58has a configuration in which three transistors of an amplificationtransistor Amp, a selection transistor Se1, and a reset transistor Rstare included as active elements for one lower substrate 54.

The lower substrate 54 is connected to between a lower electrode 55 anda floating diffusion FD, as in the example of FIG. 6. In the lowersubstrate 54, the lower electrode 55 is set to a negative voltage andthe floating diffusion FD is reset to a power supply voltage Vdd toguide the electrons to the floating diffusion FD, unlike the example ofFIG. 6.

A gate of the amplification transistor Amp is connected to the floatingdiffusion FD, as in the example of FIG. 6. This amplification transistorAmp is connected to the vertical signal line SL via the selectiontransistor Se1, and constitutes a source follower with a constantcurrent source outside the pixel. Also, a selection signal is applied toa gate of the selection transistor Se1 through a selection wiring (notillustrated). When the selection transistor Se1 is turned on, theamplification transistor Amp amplifies a potential of the floatingdiffusion FD and outputs a voltage according to the potential to thevertical signal line SL. The vertical signal line SL transfers thevoltage output from each pixel to the column signal processing circuit 5of FIG. 1.

The reset transistor Rst is connected between the power supply voltageVdd and the floating diffusion FD. Also, the reset transistor Rst resetsthe potential of the floating diffusion FD to the power supply voltageVdd when a reset signal is applied to the gate thereof through a resetwiring (not illustrated), unlike the example of FIG. 6.

In the case of this example, a technology of providing an electroninjection barrier on the lower electrode 55 side of the lower substrate54 and a hole injection barrier on the infrared electrode 57 side, forexample, to reduce a dark current can be used.

Process of Manufacturing Solid-State Imaging Device

Next, a process of manufacturing the solid-state imaging device (thepixel of FIG. 3) will be described with reference to a flowchart of FIG.8 and process diagrams of FIGS. 9A to 10B. In addition, this process isa process to be performed by a manufacturing device for manufacturing asolid-state imaging device.

First, in step S51 of FIG. 5, the manufacturing device forms thephotodiode 56, the transistors, and the wirings (including the infraredelectrode 57) in the Si substrate 51. Here, the photodiode 56, thetransistors, and the wiring layer 53 are formed in the Si substrate 51,and a top layer becomes the infrared electrode 57, as illustrated inFIG. 9A.

In step S52, the manufacturing device affixes the lower substrate 54 onthe wiring layer 53, as illustrated in FIG. 9B.

In step S53, the manufacturing device turns over the wafer (Si substrate51), as illustrated in FIG. 10A.

In step S54, the manufacturing device shaves the Si substrate 51 to athickness of several μm to form a passivation film 52, as illustrated inFIG. 10B.

In step S55, the manufacturing device performs backside processing onthe lower substrate 54.

In addition, the lower electrode 55 illustrated in FIG. 3 may be formedin the process of step S55, or may not be formed in this chip but may beprovided on the package side. In this case, affixing to the package withan electrode enables electrical conduction.

2. Second Embodiment (Backside Illumination Type Laminated CIS)

Next, the solid-state imaging device of a backside illumination typeincludes a device in which transistors/wirings, that is, a circuit ismounted in an Si substrate that is a substrate support. Such a devicewill be described.

Example of Schematic Basic Configuration of Solid-State Imaging Device

FIGS. 11A, 11B and 11C are diagrams illustrating a basic schematicconfiguration of a solid-state imaging device according to anotherembodiment of the present technology.

A solid-state imaging device illustrated in FIG. 11A includes a pixelarea 72, a control circuit 73, and a logic circuit 74 for signalprocessing that are mounted in one semiconductor chip 80. Usually, animage sensor 75 includes the pixel area 72 and the control circuit 73.

On the other hand, in a solid-state imaging device in another embodimentof the present technology, a pixel area 82 and a control circuit 83 aremounted in a first semiconductor chip portion 81, and a logic circuit 84including a signal processing circuit for signal processing is mountedin a second semiconductor chip portion 85, as illustrated in FIG. 11B.In addition, the vertical driving circuit 4, the horizontal drivingcircuit 6, and the control circuit 8 of FIG. 1, for example, areincluded in the control circuit 83. In addition, a signal processingcircuit for performing signal processing, such as correction or gain, onthe output from the output circuit 7 of FIG. 1, for example, is includedin the logic circuit 84.

On the other hand, in a solid-state imaging device in another embodimentof the present technology, a pixel area 82 is mounted on a firstsemiconductor chip portion 81, and a control circuit 83 and a logiccircuit 84 including a signal processing circuit are mounted on a secondsemiconductor chip portion 85, as illustrated in FIG. 11C.

Also, the first and second semiconductor chip portions 81 and 85 areelectrically connected to each other to constitute a solid-state imagingdevice as one semiconductor chip.

In addition, a configuration of the solid-state imaging device is notlimited to FIGS. 11B and 11C. For example, some of the control circuit83 (for example, the vertical driving circuit 4, the horizontal drivingcircuit 6, and the control circuit 8) are included in the firstsemiconductor chip portion 81, and the others of the control circuit 83are included in the second semiconductor chip portion 85. For example,the vertical driving circuit 4 and the horizontal driving circuit 6 maybe included as the some in the first semiconductor chip portion 81, andthe others may be included in the second semiconductor chip portion 85,or only the vertical driving circuit 4 (or the horizontal drivingcircuit 6) may be included in the first semiconductor chip portion 81and the others may be included in the second semiconductor chip portion85. In addition, the second semiconductor chip portion 85 may include amemory circuit that stores, for example, a signal input by the pixelarea or data of a signal processing result. For example, the secondsemiconductor chip portion 85 may include both the logic circuit 84 andthe memory circuit.

Further, in a solid-state imaging device in another embodiment of thepresent technology, three layers of semiconductor chip portions areelectrically connected to one another to constitute one semiconductorchip, as illustrated in FIGS. 12A and 12B.

In other words, in the solid-state imaging device in another embodimentof the present technology, a pixel area 82 and a control circuit 83 aremounted on a first semiconductor chip portion 81, and a logic circuit 84including a signal processing circuit that performs signal processing ismounted on a second semiconductor chip portion 85, as illustrated inFIG. 12A. Further, in the solid-state imaging device, a memory circuit87 that stores a signal input by the pixel area or data of a signalprocessing result is mounted on a third semiconductor chip portion 86,as illustrated in FIG. 12A.

Alternatively, in a solid-state imaging device in another embodiment ofthe present technology, a pixel area 82 is mounted on a firstsemiconductor chip portion 81, and a control circuit 83 and a logiccircuit 84 including a signal processing circuit are mounted on a secondsemiconductor chip portion 85, as illustrated in FIG. 12B. Further, inthe solid-state imaging device, a memory circuit 87 is mounted on athird semiconductor chip portion 86, as illustrated in FIG. 12B.

Also, the first semiconductor chip portion 81, the second semiconductorchip portion 85, and the third semiconductor chip portion 86 areelectrically connected to one another to constitute a solid-stateimaging device as one semiconductor chip.

In addition, even in the example of FIGS. 12A and 12B, in theconfiguration of each unit included in the control area, for example,some in the control circuit 83 may be included in the firstsemiconductor chip portion 81, and the others in the control circuit 83may be included in the second semiconductor chip portion 85, as in theconfiguration of the control area described above with reference toFIGS. 11A, 11B and 11C. In addition, in the example of FIGS. 12A and12B, a memory circuit may be mounted on the second semiconductor chipportion 85. In addition, a logic circuit may be mounted on the thirdsemiconductor chip portion 86. For example, both the logic circuit 84and the memory circuit may be mounted on the second semiconductor chipportion 85 or the third semiconductor chip portion 86.

As described above, the solid-state imaging devices in the otherembodiments of the present technology are configured by laminating thesemiconductor chips (semiconductor substrates). In addition, while anexample in which two layers and three layers of semiconductor chips arelaminated will be described below, the number of laminated layers is notlimited to 2 or 3, and may be 4, 5 or greater.

Example of Configuration of Pixel of Solid-State Imaging Device

FIG. 13 is a schematic view of one pixel of a solid-state imaging deviceaccording to another embodiment of the present technology.

In a pixel 2 of FIG. 13, a silicon (Si) substrate A 101 forms alaminated structure with a lower substrate 111. A photodiode 104 or atransistor is provided in the Si substrate A 101, and a passivation film102 is formed on the Si substrate A 101, as in the example of FIG. 3. Inaddition, even in the case of the example of FIG. 13, an on-chip colorfilter 35 or an OCL 36 as illustrated in FIG. 2 may be formed on theincidence surface (top in FIG. 13; back surface).

A wiring layer 103 is formed beneath the Si substrate A 101. Transistorsor wirings are provided in the wiring layer 103. In the Si substrate A101 and the wiring layer 103 beneath the Si substrate A 101, a visiblelight reading circuit 108 is formed on the right side in FIG. 13. Thevisible light reading circuit 108 is configured similar to the visiblelight reading circuit 59 of FIG. 4. In addition, an infrared lightreading circuit 109 is formed in the lower substrate 111, unlike theexample of FIG. 3.

The lower substrate 111 is a silicon (Si) substrate in which thetransistors and the wirings are formed. The lower substrate 111 isconfigured to include a wiring layer 105, an Si substrate B 106, and alower electrode 107.

The Si substrate B 106 is a thin, n-type substrate formed of Si, and atransistor, for example, is provided. Transistors or wirings areprovided in the wiring layer 105 formed on the upper side in FIG. 13 ofthe Si substrate B 106. In the Si substrate B 106 and the wiring layer105 on the Si substrate B 106, the infrared light reading circuit 109 isprovided in a position substantially overlapping the visible lightreading circuit 108. Accordingly, it is possible to decrease a size ofthe pixel.

In addition, the infrared light reading circuit 109 can be configuredsimilar to the visible light reading circuit 59 described above withreference to FIG. 4. In this case, since a buried photodiode handlingelectrons can be used, it is possible to reduce noise.

Since the infrared light is photoelectrically converted over the entireSi substrate B 106 of tens of μm to hundreds of μm rather than severalμm, a negative voltage is applied to the lower electrode 107 to collectthe infrared light in an upper n+ portion, and thus an electric field isgenerated in the Si substrate B 106.

With the configuration as described above, even in the laminatedsolid-state imaging device of a backside illumination type, the visiblelight and the infrared light can be obtained at substantially the sametime. In addition, it is possible to separately obtain the visible lightand the infrared light.

Process of Manufacturing Solid-State Imaging Device

Next, a process of manufacturing a solid-state imaging device (the pixelof FIG. 13) will be described with reference to a flowchart of FIG. 14and a process diagram of FIGS. 15A to 15E. In addition, this process isa process to be performed by a manufacturing device for manufacturing asolid-state imaging device.

First, in step S101 of FIG. 14, the manufacturing device forms aphotodiode 104, transistors, and wirings in an Si substrate A 101. Here,the photodiode 104, the transistors, and a wiring layer 103 are formedin the Si substrate A 101, as illustrated in FIG. 15A.

In step S102, the manufacturing device forms the transistors and wiringsusing a thin, n-type substrate as an Si substrate B 106. Accordingly, alower substrate 111 in which a wiring layer 105 is formed in the Sisubstrate B 106 is obtained, as illustrated in FIG. 15B.

In step S103, the manufacturing device turns over the Si substrate A 101as illustrated in FIG. 15C, and affix the Si substrate A 101 on thelower substrate 111 in an arrow P of FIG. 15D.

In step S104, the manufacturing device shaves the Si substrate A 101 toa thickness of several μm to form a passivation film 102, as illustratedin FIG. 10E.

In step S105, the manufacturing device performs backside processing onthe lower substrate 111.

In addition, the lower electrode 107 illustrated in FIG. 13 may beformed in the process of step S105, or may not be formed in this chipbut may be provided on the package side. In this case, affixing to thepackage with an electrode enables electrical conduction.

The present technology can be implemented in various other forms. Forexample, while all the pixels 2 have been described as taking thevisible light and the infrared light in the above description, theinfrared light may be acquired by one pixel in a plurality of visiblepixels (for example, four pixels).

In addition, while the example in which the visible light and theinfrared light are obtained at the same time by releasing one electronicshutter has been described in the description described above, separateelectronic shutters can be released in the visible light and theinfrared light to obtain different exposure time.

Further, while a part of the infrared light is mixed on the Si-substrateside and a part of the visible light is mixed on the lower-substrateside, correction from each other's signals is in preparation since thelights are signals at the same time in the same position. In addition,the lower substrate is described above because this lower substrate maynot have to serve as a substrate support in a technology such aslamination of three substrate layers.

In addition, the present technology, for example, is not limited toapplication to the solid-state imaging device, such as an image sensor.In other words, the present technology is applicable to all electronicapparatuses in which a solid-state imaging device is used in an imageacquisition unit (photoelectric conversion unit), such as an imagingdevice such as a digital still camera or a video camera, a portableterminal device having an imaging function, and a copier using asolid-state imaging device in an image reading unit.

3. Third Embodiment

Example of Configuration of Electronic Apparatus

FIG. 16 is a block diagram illustrating an example of a configuration ofa camera device as the electronic apparatus to which an embodiment ofthe present technology is applied.

A camera device 600 of FIG. 16 includes an optical unit 601 including,for example, a lens group, a solid-state imaging device (imaging device)602 in which each configuration of the pixel 2 described above isadopted, and a DSP circuit 603 that is a camera signal processingcircuit. In addition, the camera device 600 further includes a buffermemory 604, a CPU 605, a display unit 606, a recording unit 607, amanipulation unit 608, and a power supply unit 609. The DSP circuit 603,the buffer memory 604, the CPU 605, the display unit 606, the recordingunit 607, the manipulation unit 608, and the power supply unit 609 areconnected to one another through a bus line 610.

The optical unit 601 acquires incident light (image light) from asubject and forms an image on an imaging surface of the solid-stateimaging device 602. The solid-state imaging device 602 converts a lightamount of incident light of the image formed on the imaging surface bythe optical unit 601 into an electrical signal in units of pixels andoutputs the electrical signal as a pixel signal. The solid-state imagingdevice according to the embodiment described above may be used as thissolid-state imaging device 602. Accordingly, in the camera device 600,two solid-state imaging devices do not have to be provided since visiblelight and infrared light are obtained in one solid-state imaging device.Thus, it is possible to decrease a cost and a size of the device.

An image signal-processed by the DSP circuit 603, or the like isrecorded in the buffer memory 604. The CPU 605 controls each unit of thecamera device 600.

The display unit 606 includes, for example, a display device of a paneltype such as a liquid crystal panel or an organic electro luminescence(EL) panel, and displays a moving image or a still image captured by thesolid-state imaging device 602. The recording unit 607 records themoving image or the still image captured by the solid-state imagingdevice 602 in a recording medium, such as a video tape or a digitalversatile disk (DVD).

The manipulation unit 608 issues a manipulation instruction for variousfunctions of the camera device 600 under a manipulation by the user. Thepower supply unit 609 appropriately supplies various supply voltagesthat are operation voltages of the DSP circuit 603, the buffer memory604, the CPU 605, the display unit 606, the recording unit 607, and themanipulation unit 608 to these supply targets.

In addition, in the present specification, the steps describing theseries of processes described above include not only processes that areperformed in time series in the described order, but also processes thatare executed in parallel or individually, instead of being necessarilyprocessed in time series.

Further, embodiments in the present disclosure are not limited to theembodiments described above and various changes can be made withoutdeparting from the gist of the present disclosure.

In addition, the respective steps described in the above-describedflowchart can be not only executed by one device, but also executed incooperation by a plurality of devices.

Further, when a plurality of processes are to be included in one step,the plurality of processes included in one step can be not only executedby one device, but also executed in cooperation by a plurality ofdevices.

Further, the configuration described above as one device (or processingunit) may be divided into a plurality of devices (or processing units).On the contrary, the configuration described above as a plurality ofdevices (or processing units) may be combined into one device (orprocessing unit). Further, it is understood that a configuration otherthan the configuration described above may be added to the configurationof each device (or each processing unit). Further, if a configuration oran operation of an entire system is substantially the same, a part ofthe configuration of any device (or processing unit) may be included ina configuration of another device (or another processing unit). In otherwords, the present technology is not limited to the embodimentsdescribed above and various changes can be made without departing fromthe gist of the present technology.

While the preferred embodiments of the present disclosure have beendescribed in detail with reference to the accompanying drawings, thedisclosure is not limited to such examples. It is apparent that variousvariations or modifications can be conceived by those skilled in the artin the category of technical ideas of the claims, and it is understoodthat the variations or modifications belong to the technical scope ofthe present disclosure.

In addition, the present technology can also take the followingconfigurations.

(1) A solid-state imaging device including an Si substrate in which aphotoelectric conversion unit that photoelectrically converts visiblelight incident from a back surface side is formed; and a lower substrateprovided under the Si substrate and configured to photoelectricallyconvert infrared light incident from the back surface side.

(2) The solid-state imaging device according to (1), wherein the lowersubstrate is formed of a compound semiconductor.

(3) The solid-state imaging device according to (1) or (2), wherein aninfrared electrode comes in contact with the Si substrate side of thelower substrate, and a lower electrode comes in contact with the outerside of the lower substrate.

(4) The solid-state imaging device according to any one of (1) to (3),wherein a visible light reading circuit configured to read the visiblelight and an infrared light reading circuit configured to read theinfrared light are formed in the Si substrate.

(5) The solid-state imaging device according to (3) or (4), wherein theinfrared electrode is formed in a ring shape.

(6) The solid-state imaging device according to any one of (3) to (5),wherein the visible light reading circuit and the infrared light readingcircuit are formed in a position substantially overlapping the infraredelectrode.

(7) The solid-state imaging device according to (3), wherein theinfrared electrode is formed to be transparent.

(8) The solid-state imaging device according to (1), wherein the lowersubstrate is formed of silicon, and includes transistors and wirings.

(9) The solid-state imaging device according to (8), wherein the lowersubstrate is an n-type substrate.

(10) The solid-state imaging device according to (8) or (9), wherein theSi substrate and the lower substrate form a laminated structure.

(11) The solid-state imaging device according to (10), wherein a visiblelight reading circuit configured to read the visible light is formed inthe Si substrate, and an infrared light reading circuit configured toread the infrared light is formed in the lower substrate.

(12) The solid-state imaging device according to (10) or (11), whereinthe infrared light reading circuit is provided in a positionsubstantially overlapping the visible light reading circuit.

(13) A method of manufacturing a solid-state imaging device, the methodincluding: forming, by a manufacturing device, a photoelectricconversion unit that photoelectrically converts visible light incidentfrom a back surface side, in an Si substrate; and affixing, by amanufacturing device, a lower substrate that photoelectrically convertsinfrared light incident from the back surface side, under the Sisubstrate.

(14) An electronic apparatus including: a solid-state imaging deviceincluding an Si substrate in which a photoelectric conversion unit thatphotoelectrically converts visible light incident from a back surfaceside is formed, and a lower substrate provided under the Si substrateand configured to photoelectrically convert infrared light incident fromthe back surface side; a signal processing circuit configured to processan output signal output from the solid-state imaging device; and anoptical system configured to cause the visible light and the infraredlight to be incident on the solid-state imaging device.

(15) The electronic apparatus according to (14), wherein the lowersubstrate is formed of a compound semiconductor.

(16) The electronic apparatus according to (14), wherein an infraredelectrode comes in contact with the Si substrate side of the lowersubstrate, and a lower electrode comes in contact with the outer side ofthe lower substrate.

(17) The electronic apparatus according to any one of (14) to (16),wherein a visible light reading circuit configured to read the visiblelight and an infrared light reading circuit configured to read theinfrared light are formed in the Si substrate.

(18) The electronic apparatus according to (16) or (17), wherein theinfrared electrode is formed in a ring shape.

(19) The electronic apparatus according to (17) or (18), wherein thevisible light reading circuit and the infrared light reading circuit areformed in a position substantially overlapping the infrared electrode.

(20) The electronic apparatus according to (16), (17) or (19), whereinthe infrared electrode is formed to be transparent.

(21) The electronic apparatus according to (14), wherein the lowersubstrate is formed of silicon, and includes transistors and wirings.

It should be understood by those skilled in the art that variousmodifications, combinations, sub-combinations and alterations may occurdepending on design requirements and other factors insofar as they arewithin the scope of the appended claims or the equivalents thereof.

What is claimed is:
 1. An imaging device comprising; a first substrateconfigured to absorb at least a portion of visible light incident to afirst side of the first substrate; a passivation film disposed on thefirst side of the first substrate; a second substrate configured toconvert at least infrared light into a first electric signal, whereinthe second substrate is an indium gallium arsenide (InGaAs) substrate; acontact layer disposed between a second side of the first substrate anda first side of the second substrate, wherein the second side of thefirst substrate is opposite the first side of the first substrate; afirst metal disposed on a second side of the second substrate, whereinthe second side of the second substrate is opposite the first side ofthe second substrate; and a readout circuit coupled to the secondsubstrate and configured to receive the first electric signal.
 2. Theimaging device according to claim 1, wherein the first metal receives afirst voltage and applies the first voltage to the second substrate. 3.The imaging device according to claim 1, further comprising a secondmetal bonded to the second substrate.
 4. The imaging device according toclaim 3, wherein the second metal is electrically connected to thecontact layer.
 5. The imaging device according to claim 1, wherein thecontact layer receives a second voltage.
 6. The imaging device accordingto claim 5, wherein the second voltage is lower than a first voltage. 7.The imaging device according to claim 1, wherein the first substrate isa silicon substrate.
 8. The imaging device according to claim 1, furthercomprising a transfer transistor, a reset transistor, an amplifiertransistor.
 9. The imaging device according to claim 1, wherein thefirst substrate includes a photodetector configured to convert theportion of the visible light into a second electric signal.
 10. Theimaging device according to claim 1, wherein the second substrate isconfigured to convert only infrared light into the first electricsignal.
 11. The imaging device according to claim 5, wherein the secondvoltage is a ground voltage or a common voltage.
 12. The imaging deviceaccording to claim 1, further comprising a second metal disposed on thesecond side of the second substrate and electrically connected to thecontact layer.
 13. The imaging device according to claim 12, wherein thefirst metal receives a first voltage and applies the first voltage tothe second substrate.
 14. The imaging device according to claim 13,wherein the first metal receives the first voltage from the readoutcircuit.
 15. The imaging device according to claim 13, wherein thesecond metal receives a second voltage.
 16. The imaging device accordingto claim 15, wherein the second voltage is lower than the first voltage.17. The imaging device according to claim 16, wherein the second voltageis a ground voltage or a common voltage.